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? semiconductor components industries, llc, 2016 september, 2016 ? rev. 1 1 publication order number: ncp12510/d ncp12510 current-mode pwm controller for off-line power supplies the ncp12510 is a highly integrated pwm controller capable of delivering a rugged and high performance offline power supply in a tiny tsop?6 package. with a voltage supply range up to 35 v, the controller hosts a jittered 65?khz or 100?khz switching circuitry operated in peak current mode control. when the power on the secondary side starts decreasing, the controller automatically folds back its switching frequency down to a minimum level of 26 khz. as the power further goes down, the part enters skip cycle while limiting the peak current. over power protection (opp) is a difficult exercise especially when no?load standby requirements drive the converter specifications. the on semiconductor proprietary integrated opp allows harness the maximum delivered power without affecting the standby performance simply via two external resistors. an over voltage protection (ovp) input is also combined on the same pin and protects the whole circuitry in case of optocoupler destruction or adverse open loop operation. finally, a timer?based short?circuit protection offers the best protection scheme, allowing precisely select the protection trip point without caring of a loose coupling between the auxiliary and the power windings. ncp12510 is improved and pin compatible controller based on very popular flyback controller ncp1250. features ? fixed?frequency 65 khz or 100 khz current?mode control operation ? frequency foldback down to 26 khz and skip?cycle in light load conditions ? frequency jittering in normal and frequency foldback modes ? internal and adjustable over power protection (opp) circuit ? auto?recovery over voltage protection (ovp) on the vcc pin ? internal and adjustable slope compensation ? internal fixed 4 ms soft?start ? auto?recovery or latched short?circuit protection ? pre?short ready for latched ocp version ? ovp/otp latch input for improved robustness ? +300 ma/ ?500 ma source/sink drive capability ? improved consumption ? improved reset time in latch state ? high robustness and high esd capabilities ? eps 2.0 compliant ? this is a pb?free device typical applications ? ac?dc converters for tvs, set?top boxes and dvd players ? offline adapters for notebooks and netbooks pin connections 1 3 cs gnd 2 opp/latch 4 drv 6 (top view) 5 v cc tsop?6 (sot23?6) sn suffix case 318g style 13 marking diagram fb www. onsemi.com (note: microdot may be in either location) 1 5dxayw 1 5dx = specific device code x = a, 2, j, or k a = assembly location y = year w = work week = pb?free package see detailed ordering, marking and shipping information on page 2 of this data sheet. ordering information
ncp12510 www. onsemi.com 2 figure 1. typical application example table 1. pin description pin no pin name function pin description 1 gnd ? the controller ground. 2 fb feedback pin hooking an optocoupler collector to this pin will allow regulation. 3 opp/latch adjust the over power protection latches off the part a resistive divider from the auxiliary winding to this pin sets the opp compensation level during the on?time. when the voltage exceeds a certain level at turn off, the part is fully latched off. 4 cs current sense + slope compensation this pin monitors the primary peak current but also offers a means to introduce slope compensation. 5 v cc supplies the controller ? protects the ic this pin is connected to an external auxiliary voltage. when the v cc exceeds a certain level, the part enters an auto?recovery hiccup. 6 drv driver output the driver output to an external mosfet gate. table 2. device options and ordering information controller (note 1) package marking ocp protection ovp/otp protection switching frequency package shipping ? NCP12510ASN65T1G 5da latched latched 65 khz tsop?6 (pb?free) 3000 / tape & reel ncp12510bsn65t1g 5d2 auto?recovery latched 65 khz ncp12510asn100t1g 5dj latched latched 100 khz ncp12510bsn100t1g 5dk auto?recovery latched 100 khz ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. 1. other options available upon customer request.
ncp12510 www. onsemi.com 3 figure 2. internal circuit architecture 65 / 100 khz oscillator clamp drv v cc and logic management vcc + v ovp gnd opp/ latch + v latch up counter to 4 cs fb v fb(open) r eq k ratio frequency foldback r ramp peak current freeze soft-start + v limit +v opp v opp up counter to 8 jittering _ + + _ + _ rst t latch(del) t latch(blank) t ovp(del) + _ + v skip s r q q d max leb v limit + _ + fault timer ocp fault rst rst drv pulse v opp drv pulse r s q q error flag drv pulse drv pulse latch / auto-revery management note: depend on ic option ovp/otp latch v cc(ovp) ic stop drv stop v cc(ovp) v cc(min) ic start ic stop ic reset ocp fault ovp/otp latch pre-short latch / auto- recovery mode drv stop latch / auto- recovery mode internal supply pre-short 1 st drv pulse during ic start v cc(min) s r q q (for ocp&uvlo latched option ) armed flag ic in regulation fb@gnd ic in regulation v cc(on)
ncp12510 www. onsemi.com 4 table 3. maximum ratings table symbol rating value unit v cc power supply voltage, vcc pin, continuous voltage ?0.3 to 35 v v drv(tran) maximum drv pin voltage when drv in h state, transient voltage (note 1) ?0.3 to v cc + 0.3 v v cs , v fb , v opp maximum voltage on low power pins cs, fb and opp (note 2) ?0.3 to 5.5 v v opp(tran) maximum negative transient voltage on opp pin (note 2) ?1 v i source,max maximum sourced current, pulsed width < 800 ns 0.6 a i sink,max maximum sinked current, pulse width < 800 ns 1.0 a i opp maximum injected negative current into the opp pin (pin 3) ?2 ma r j?a thermal resistance junction?to?air 360 c/w t j,max maximum junction temperature 150 c storage temperature range ?60 to +150 c hbm human body model esd capability per jedec jesd22?a114f (all pins) 4 kv cdm charged?device model esd capability per jedec jesd22?c101e 750 v stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. the transient voltage is a voltage spike injected to drv pin being in high state. maximum transient duration is 100 ns. 2. see the figure 3 for detailed specification of transient voltage. 3. this device contains latch?up protection and exceeds 100 ma per jedec standard jesd78. figure 3. negative pulse for opp pin during on?time and positive pulse for all low power pins 500 ns -1 v v opp, max 0v v opp v opp,max = -0.75 v, t j =-25 c v opp,max = -0.65 v, t j =25 c v opp,max =-0.3v,t j =125 c C worst case v opp must stay between 0v and C0.3 v for a linear opp operation t v opp (t) on-time 500 ns 7.5 v C 5.5 v C 0v v cs v fb v opp t soa max dc voltage max transient voltage cycle-by-cycle max current during overshoot can 't exceed 3 ma
ncp12510 www. onsemi.com 5 table 4. electrical characteristics (for typical values t j = 25 c, for min/max values t j = ?40 c to +125 c, v cc = 12 v unless otherwise noted) symbol rating pin min typ max unit supply section v cc(on) v cc increasing level at which driving pulses are authorized 5 16 18 20 v v cc(min) v cc decreasing level at which driving pulses are stopped 5 8.3 8.9 9.5 v v cc(hyst) hysteresis v cc(on) ? v cc(min) 5 7.7 ? ? v v cc(reset) latched state reset voltage 5 ? 8.6 ? v v cc(reset_ hyst) defined hysteresis between minimum and reset voltage v cc(min) ? v cc(reset) 5 0.15 0.30 0.45 v v cc(latch_hyst) defined hysteresis for hiccupping between two voltage levels in latch mode 5 ? 0.55 ? v i cc1 start?up current (v cc(on) ? 100 mv) 5 ? 6 10 a i cc2 internal ic consumption with v fb = 3.2 v, f sw = 65 khz and c l = 0 nf internal ic consumption with v fb = 3.2 v, f sw = 100 khz and c l = 0 nf 5 ? 1.0 1.1 1.4 1.5 ma i cc3 internal ic consumption with v fb = 3.2 v, f sw = 65 khz and c l = 1 nf internal ic consumption with v fb = 3.2 v, f sw = 100 khz and c l = 1 nf 5 ? 1.7 2.3 2.7 3.0 ma i cc(no?load) internal consumption in skip mode ? non switching, v fb = 0 v 5 ? 300 ? a i cc(fault) internal consumption in fault mode ? during going?down v cc cycle, v fb = 4 v 5 ? 370 ? a i cc(standby) internal ic consumption in skip mode for 65 khz version (v cc = 14 v, driving a typical 7?a/600?v mosfet, includes opto current) ? (note 4) 5 ? 420 ? a drive output t r output voltage rise?time @ c l = 1 nf, 10?90% of output signal 6 ? 40 ? ns t f output voltage fall?time @ c l = 1 nf, 10?90% of output signal 6 ? 30 ? ns r oh source resistance, v cc = 12 v, i drv = 100 ma 6 ? 28 ? r ol sink resistance, v cc = 12 v, i drv = 100 ma 6 ? 7 ? i source peak source current, v gs = 0 v 6 ? 300 ? ma i sink peak sink current, v gs = 12 v 6 ? 500 ? ma v drv(low) drv pin level at v cc = v cc(min) + 100 mv with a 33 k resistor to gnd 6 8 ? ? v v drv(high) drv pin level at v cc = v ovp ? 100 mv (drv unloaded) 6 10 12 14 v current comparator v limit maximum internal current set point ? t j = 25 c ? pin 3 grounded maximum internal current set point ? t j = ?40 c to 125 c ? pin 3 grounded 4 0.744 0.720 0.8 0.8 0.856 0.880 v v cs(fold) internal voltage setpoint for frequency foldback trip point ? 59% of v limit 4 ? 475 ? mv v cs(freeze) internal peak current setpoint freeze ( 31% of v limit ) 4 ? 250 ? mv t del propagation delay from cs pin to drv output 4 ? 50 80 ns t leb leading edge blanking duration 4 ? 300 ? ns t ss internal soft?start duration activated upon startup or auto?recovery 4 ? 4 ? ms i opps set point decrease for pin 3 grounded 3 ? 0 ? % i oppo set point decrease for pin 3 biased to ?250 mv 3 ? 31.3 ? % i oopv voltage set point for pin 3 biased to ?250 mv, t j = 25 c voltage set point for pin 3 biased to ?250 mv, t j = ?40 to 125 c 3 0.51 0.50 0.55 0.55 0.60 0.62 v internal oscillator f osc(nom) oscillation frequency (65 khz version) oscillation frequency (100 khz version) ? 61 92 65 100 71 108 khz d max maximum duty?ratio ? 76 80 84 % f jitter frequency jittering in percentage of f osc ? jitter is kept even in foldback mode ? ? 5 ? % 4. application parameter for information only. 5. 1?m resistor is connected from pin 4 to the ground for the measurement.
ncp12510 www. onsemi.com 6 table 4. electrical characteristics (for typical values t j = 25 c, for min/max values t j = ?40 c to +125 c, v cc = 12 v unless otherwise noted) symbol unit max typ min pin rating internal oscillator f swing swing frequency ? ? 240 ? hz feedback section r eq internal equivalent feedback resistance 2 ? 29 ? k k ratio fb pin to current set point division ratio ? ? 4 ? ? v fb(freeze) feedback voltage below which the peak current is frozen 2 ? 1.2 ? v v fb(limit) feedback voltage corresponding with maximum internal current set point 2 ? 3.2 ? v v fb(open) internal pull?up voltage on fb pin 2 ? 4 ? v frequency foldback v fold(start) frequency foldback level on the fb pin ? 59% of maximum peak current ? ? 1.9 ? v f trans minimum operating frequency ? 22 26 30 khz v fold(end) end of frequency foldback feedback level, f sw = f trans ? ? 1.5 ? v v skip skip?cycle level voltage on the feedback pin ? ? 0.8 ? v v skip(hyst) hysteresis on the skip comparator ? ? 50 ? mv internal slope compensation v ramp internal ramp level @ 25 c (note 5) 4 ? 2.5 ? v r ramp internal ramp resistance to cs pin 4 ? 20 ? k protections v latch latching level input on opp/latch pin 3 2.85 3.0 3.15 v t latch(blank) blanking time after drive output turn off 3 ? 1 ? s t latch(count) number of clock cycles before latch is confirmed 3 ? 4 ? t latch(del) ovp/otp delay time constant before latch is confirmed 3 ? 600 ? ns v ovp over voltage protection on the vcc pin 5 24.0 25.5 27.0 v t ovp(del) delay time constant before ovp on vcc is confirmed 5 ? 20 ? s t fault internal fault timer duration ? 100 115 130 ms 4. application parameter for information only. 5. 1?m resistor is connected from pin 4 to the ground for the measurement.
ncp12510 www. onsemi.com 7 typical characteristics figure 4. figure 5. temperature ( c) temperature ( c) 125 100 75 50 25 0 ?25 ?50 16.0 16.5 17.0 17.5 18.0 19.0 19.5 20.0 125 100 75 50 25 0 ?25 ?50 8.0 8.1 8.3 8.4 8.5 8.7 8.8 9.0 figure 6. figure 7. temperature ( c) temperature ( c) 125 100 75 50 25 0 ?25 ?50 8.4 8.5 8.7 8.8 8.9 9.1 9.2 9.4 125 100 75 50 25 0 ?25 ?50 100 150 200 250 300 400 450 500 figure 8. figure 9. temperature ( c) temperature ( c) 125 100 75 50 25 0 ?25 ?50 8.8 8.9 9.0 9.1 9.2 9.4 9.5 9.6 125 100 75 50 25 0 ?25 ?50 200 300 400 500 600 700 800 900 v cc(on) (v) v cc(reset) (v) v cc(min) (v) v cc(reset_hyst) (mv) v cc(hyst) (v) v cc(latch_hyst) (v) 18.5 8.2 8.6 8.9 8.6 9.0 9.3 350 9.3
ncp12510 www. onsemi.com 8 typical characteristics figure 10. figure 11. temperature ( c) temperature ( c) 125 100 75 50 25 0 ?25 ?50 1 2 3 4 5 7 8 10 125 100 75 50 25 0 ?25 ?50 100 200 250 300 400 500 figure 12. figure 13. temperature ( c) temperature ( c) 125 100 75 50 25 0 ?25 ?50 0.6 0.7 0.9 1.0 1.1 1.3 1.4 1.6 125 100 75 50 25 0 ?25 ?50 100 150 200 250 300 400 450 500 figure 14. figure 15. temperature ( c) adapter output current (a) 125 100 75 50 25 0 ?25 ?50 1.4 1.5 1.7 1.8 1.9 2.2 2.3 2.4 3.0 2.5 2.0 1.5 3.5 1.0 0.5 0 0 0.5 1.0 1.5 2.0 3.0 3.5 4.0 i cc1 ( a) i cc(no?load) ( a) i cc2 (ma) i cc(fault) ( a) i cc3 (ma) i cc (ma) 6 150 350 450 0.8 1.2 1.5 350 2.0 9 1.6 2.1 2.5 65 khz 65 khz v in = 120 vac
ncp12510 www. onsemi.com 9 typical characteristics figure 16. figure 17. temperature ( c) temperature ( c) 125 100 75 50 25 0 ?25 ?50 15 20 25 30 40 50 60 65 125 100 75 50 25 0 ?25 ?50 10 15 20 25 30 35 40 50 figure 18. figure 19. temperature ( c) temperature ( c) 125 100 75 50 25 0 ?25 ?50 5 10 20 25 30 40 45 55 125 100 75 50 25 0 ?25 ?50 4 6 8 10 12 14 16 figure 20. figure 21. temperature ( c) temperature ( c) 125 100 75 50 25 0 ?25 ?50 0 5 10 15 20 30 35 40 125 100 75 50 25 0 ?25 ?50 2 4 6 10 14 16 18 22 t r (ns) r oh ( ) t f (ns) v drv(low) ( ) r ol ( ) v drv(high) ( ) 45 45 15 35 50 25 35 55 8 12 20
ncp12510 www. onsemi.com 10 typical characteristics figure 22. figure 23. temperature ( c) temperature ( c) 125 100 75 50 25 0 ?25 ?50 0.65 0.70 0.75 0.80 0.85 0.95 1.00 125 100 75 50 25 0 ?25 ?50 15 20 30 35 40 50 55 figure 24. figure 25. temperature ( c) temperature ( c) 125 100 75 50 25 0 ?25 ?50 300 400 450 550 650 125 100 75 50 25 0 ?25 ?50 180 200 220 240 260 300 320 figure 26. figure 27. temperature ( c) temperature ( c) 125 100 75 50 25 0 ?25 ?50 150 175 200 225 250 300 325 350 125 100 75 50 25 0 ?25 ?50 2.0 2.5 3.0 3.5 4.0 5.0 5.5 6.0 v limit (v) t del (ns) v cs(fold) (mv) t leb (ns) v cs(freeze) (mv) t ss (ms) 0.90 25 45 350 500 600 280 275 4.5
ncp12510 www. onsemi.com 11 typical characteristics figure 28. figure 29. temperature ( c) temperature ( c) 125 100 75 50 25 0 ?25 ?50 0.1 0.2 0.3 0.5 0.6 0.9 1.0 125 100 75 50 25 0 ?25 ?50 75 80 90 95 100 110 115 125 figure 30. figure 31. temperature ( c) temperature ( c) 125 100 75 50 25 0 ?25 ?50 15 25 30 40 50 125 100 75 50 25 0 ?25 ?50 65 70 75 80 85 90 95 figure 32. figure 33. temperature ( c) temperature ( c) 125 100 75 50 25 0 ?25 ?50 45 50 55 60 65 75 80 90 125 100 75 50 25 0 ?25 ?50 225 235 245 255 265 275 285 295 i oppv (v) f osc(nom) (khz) i oppo (%) d max (%) f osc(nom) (khz) f swing (hz) 0.7 85 105 120 20 35 45 70 0.4 0.8 85 65 khz 100 khz
ncp12510 www. onsemi.com 12 typical characteristics figure 34. figure 35. temperature ( c) temperature ( c) 125 100 75 50 25 0 ?25 ?50 15 20 25 30 35 40 45 125 100 75 50 25 0 ?25 ?50 1.2 1.6 1.8 2.0 2.4 2.8 figure 36. figure 37. temperature ( c) temperature ( c) 125 100 75 50 25 0 ?25 ?50 1.5 3.5 4.5 5.5 6.5 7.5 125 100 75 50 25 0 ?25 ?50 0.8 1.0 1.2 1.4 1.6 2.0 2.2 2.4 figure 38. figure 39. temperature ( c) temperature ( c) 125 100 75 50 25 0 ?25 ?50 0.2 0.4 0.6 0.8 1.0 1.6 1.8 2.0 125 100 75 50 25 0 ?25 ?50 0.2 0.4 0.6 0.8 1.0 1.2 1.4 r eq (k ) v fold(start) (v) k ratio (?) v fold(end) (v) v fb(freeze) (v) v skip (v) 1.4 2.2 2.6 2.5 1.8 1.4 1.2
ncp12510 www. onsemi.com 13 typical characteristics figure 40. figure 41. temperature ( c) temperature ( c) 125 100 75 50 25 0 ?25 ?50 30 35 40 45 50 60 65 70 125 100 75 50 25 0 ?25 ?50 24.5 25.5 26.0 26.5 27.0 27.5 figure 42. figure 43. temperature ( c) temperature ( c) 125 100 75 50 25 0 ?25 ?50 20 24 26 30 32 34 125 100 75 50 25 0 ?25 ?50 100 105 110 115 120 125 130 figure 44. temperature ( c) 125 100 75 50 25 0 ?25 ?50 1.5 2.0 2.5 3.0 3.5 4.0 4.5 v skip(hyst) (mv) v ovp (v) f trans (khz) t fault (ms) v latch (v) 55 25.0 22 28
ncp12510 www. onsemi.com 14 application information introduction ncp12510 implements a standard current mode architecture where the switch?off event is dictated by the peak current set point. this component represents the ideal candidate where low part?count and cost effectiveness are the key parameters, particularly in low?cost ac?dc adapters, open?frame power supplies etc. updated controller, the ncp12510 packs all the necessary components normally needed in today modern power supply designs, bringing several enhancements such as a non?dissipative opp, ovp/otp implementation, short?circuit protection with pre?short ready for latched version and improved consumption, robustness and esd capabilities. ? current?mode operation with internal slope compensation: implementing peak current mode control at a 65 or 100 khz switching frequency, the ncp12510 offers an internal slope compensation signal that can easily by summed up to the sensed current. sub harmonic oscillations can thus be fought via the inclusion of a simple resistor in series with the current?sense information. ? internal opp: by routing a portion of the negative voltage present during the on?time on the auxiliary winding to the dedicated opp pin (pin 3), the user has a simple and non?dissipative means to alter the maximum peak current set point as the bulk voltage increases. if the pin is grounded, no opp compensation occurs. if the pin receives a negative voltage, then a peak current is reduced down. ? low startup and standby current: reaching a low no?load standby power always represents a difficult exercise when the controller draws a significant amount of current during startup. the ncp12510 brings improved consumption to easing the design of low standby power adapters. ? emi jittering: an internal low?frequency modulation signal varies the pace at which the oscillator frequency is modulated. this helps spreading out energy in conducted noise analysis. to improve the emi signature at low power levels, the jittering is kept in frequency foldback mode (light load conditions). ? frequency foldback capability: a continuous flow of pulses is not compatible with no?load/light?load standby power requirements. to excel in this domain, the controller observes the feedback pin and when it reaches a level of v fold(start) , it starts reduce switching frequency. when the feedback level reaches v fold(end) , the frequency hits its lower stop at f trans . when the feedback pin goes further down and reaches v fb(freeze) , the peak current setpoint is internally frozen. below this point, if power continues to drop, the controller enters classical skip?cycle mode, as both frequency and peak current are frozen. ? internal soft?start: a soft?start precludes the main power switch from being stressed upon start?up. the soft?start duration is internally fixed for time t ss and it is activated during new startup sequence or during recovering after auto?recovery double hiccup. ? latch input: the controller includes a latch input (pin 3) that can be used to sense an over voltage or an over temperature event on the adapter. if this pin is brought higher than the internal reference voltage v latch for four consecutive cycles, then the circuit is latched off ? v cc hiccups from v cc(min) voltage level with hysteresis v cc(latch_hyst) = 550 mv typically, until a reset occurs. the latch reset occurs when the user disconnects the adapter from the mains and lets the v cc falls below the v cc(reset) level. for the c version, despite an ovp/otp detection, the circuit autorecovers and never latches. ? auto?r ecovery ovp on v cc : an ovp protects the circuit against v cc runaways. if the fault is present at least for time t ovp(del) then the ovp is validated and the controller enters double hiccup mode. when the v cc returns to a nominal level, the controller resumes operation. ? short?cir cuit protection: short?circuit and especially overload protections are difficult to implement when a strong leakage inductance between auxiliary and power windings affects the transformer (the aux winding level does not properly collapse in presence of an output short). in this controller, every time the internal maximum peak current limit v limit is activated (or less when opp is used), an error flag is asserted and a time period starts thanks to an internal timer. when the timer has elapsed while a fault is still present, the controller is latched or enters an auto?recovery mode, depending on the selected ocp option. please note that with the latched ocp&uvlo option, the part becomes sensitive to the first uvlo event during the start?up sequence. any other uvlo events are ignored afterwards ? auto?recovery operation. with the first drive pulse is generated armed flag. armed flag is reset after the first successful start?up sequence (the controller gets into regulation). this is to pass the pre?short test at power up: 1. if the internal armed flag is active and an uvlo event is sensed, the part is immediately latched. 2. if an uvlo signal is detected but the armed flag is not asserted, double?hiccup auto?recovery occurs. 3. if the controller gets into regulation, the armed flag is reset. then uvlo event is sensed, the part is in auto?recovery operation.
ncp12510 www. onsemi.com 15 start?up sequence the ncp12510 start?up voltage is made purposely high to permit large energy storage in a small v cc capacitor value. this helps operate with a small start?up current which, together with a small v cc capacitor, will not hamper the start?up time. to further reduce the standby power, the start?up current of the controller is extremely low, below 10 a. the start?up resistor can therefore be connected to the bulk capacitor or directly to the mains input voltage to further reduce the power dissipation. r start-up aux. winding + + + c bulk c vcc vcc input mains figure 45. the startup resistor can be connected to the input mains for further power dissipation reduction. the first step starts with the calculation of the needed vcc capacitor which will supply the controller which it operates until the auxiliary winding takes it over . experience shows that this time t 1 can be between 5 and 20 ms. if we consider we need at least an ener gy reservoir for a t 1 time of 10 ms, the vcc capacitor must be larger than: c vcc i cc t 1 v cc(on) v cc(min) 1.7 m 10 m 18 8.9 1.9 f (eq. 1) let us select a 2.2 f capacitor at first and experiments in the laboratory will let us know if we were too optimistic for the time t 1 . the vcc capacitor being known, we can now evaluate the charging current we need to bring the v cc voltage from 0 v to the v cc(on) of the ic. this current has to be selected to ensure a start?up at the lowest mains (85 v rms ) to be less than 3 s (2.5 s for design margin): i charge v cc(on) c vcc t start up 18 2.2 2.5 16 a (eq. 2) if we account for the 10 a (maximum) that will flow to the controller, then the total charging current delivered by the start?up resistor must be 26 a. if we connect the start?up network to the mains (half?wave connection then), we know that the average current flowing into this start?up resistor will be the smallest when v cc reaches the v cc(on) of the controller: i cvcc,min v ac,rms 2 v cc(on) r start up (eq. 3) to make sure this current is always greater than 26 a, then, the minimum value for r start?up can be extracted: r start up v ac,rms 2 v cc(on) i cvcc(min) 85 2 18 26 779 k (eq. 4 ) this calculation is purely theoretical, considering a constant charging current. in reality, the take over time can be shorter (or longer!) and it can lead to a reduction of the vcc capacitor. thus, a decrease in charging current and an increase of the start?up resistor can be experimentally tested, for the benefit of standby power. laboratory experiments on the prototype are thus mandatory to fine tune the converter. if we chose the 750 k resistor as suggested by equation 4, the dissipated power at high line amounts to: p r start up,max v ac,peak 2 4 r start up 230 2
2 4 750 k 35 mw (eq. 5) now that the first vcc capacitor has been selected, we must ensure that the self?supply does not disappear when in no?load conditions. in this mode, the skip?cycle can be so deep that refreshing pulses are likely to be widely spaced, inducing a large ripple on the vcc capacitor. if this ripple is too large, chances exist to touch the v cc(min) and reset the controller into a new start?up sequence. a solution is to grow this capacitor but it will obviously be de trimental to the start?up time. the option offered in figure 45 elegantly solves this potential issue by adding an extra capacitor on the auxiliary winding. however, this component is separated
ncp12510 www. onsemi.com 16 from the vcc pin via a simple diode. you therefore have the ability to grow this capacitor as you need to ensure the self?supply of the controller without affecting the start?up time and standby power. internal over power protection there are several known ways to implement over power protection (opp), all suffering from particular problems. these problems range from the added consumption burden on the converter or the skip?cycle disturbance brought by the current?sense offset. a way to reduce the power capability at high line is to capitalize on the negative voltage swing present on the auxiliary diode anode. during the turn?on time, this point dips to ?n 2 v bulk , where n 2 being the turns ratio between the primary winding and the auxiliary winding. the negative plateau observed on figure 46 will have amplitude depending on the input voltage. the idea implemented in this chip is to sum a portion of this negative swing with the internal voltage reference v limit = 0.8 v. for instance, if the voltage swings down to ?150 mv during the on?time, then the internal peak current set point will be fixed to the value 0.8 v ? 0.150 v = 650 mv. the adopted principle appears in figure 47 and shows how the final peak current set point is constructed. let?s assume we need to reduce the peak current from 2.5 a at low line, to 2 a at high line. this corresponds to a 20% reduction or a set point voltage of 640 mv. to reach this level, then the negative voltage developed on the opp pin must reach: v opp 0.8 v limit v limit 0.64 0.8 ?160 mv (eq. 6) 1 v(24) 464u 472u 480u 488u 496u time in seconds ?40.0 ?20.0 0 20.0 40.0 v(24) in volts plot1 1 ?n 2 v bulk n 1 (v out +v f ) on? time off? time 1 v(24) 464u 472u 480u 488u 496u time in seconds ?40.0 ?20.0 0 20.0 40.0 v(24) in volts plot1 1 ?n 2 v bulk n 1 (v out +v f ) on? time off? time figure 46. the signal obtained on the auxiliary winding swings negative during the on?time.
ncp12510 www. onsemi.com 17 opp r oppl v cc r oppu aux. winding + i opp ref = 0.8v + v opp v limit =0.8v 7% + + _ driver reset cs r sense k1 k2 sum ref (v opp is negative) this point will be adjusted to reduce the ?ref at hi line to the desired level swings to: n 1 v out during t off -n 2 v in during t on figure 47. the opp circuitry affects the maximum peak current set point by summing a negative voltage to the internal voltage reference. let us assume that we have the following converter characteristics: v out = 19 v v in = 85 to 265 v rms n 1 = n p :n s = 1:0.25 n 2 = n p :n aux = 1:0.18 given the turns ratio between the primary and the auxiliary windings, the on?time voltage at high line (265 v rms ) on the auxiliary winding swings down to: v aux ?n 2 v in,max ?0.18 375 ?67.5 v (eq. 7) to obtain a level as imposed by equation 7, we need to install a divider featuring the following ratio: div v opp v aux ?0.16 ?67.5 2.4 m (eq. 8) if we arbitrarily fix the pull?down resistor r oppl to 1 k , then the upper resistor can be obtained by: r oppu v aux v opp v opp r oppl ?67.5 0.16 ?0.16 1k 422 k (eq. 9 ) if we now plot the peak current set point obtained by implementing the recommended resistor values, we obtain the following curve, as shown in figure 48. v bulk peak current setpoint 100% 80% 375 v figure 48. the peak current regularly reduces down to 80% at 375 vdc.
ncp12510 www. onsemi.com 18 the opp pin is surrounded by zener diodes stacked to protect the pin against esd pulses. these diodes accept some peak current in the avalanche mode and are designed to sustain a certain amount of energy. on the other side, negative injection into these diodes (or forward bias) can cause substrate injection which can lead to an erratic circuit behavior. to avoid this problem, the pin is internal clamped slightly below ?300 mv which means that if more current is injected before reaching the esd forward drop, then the maximum peak reduction is kept to 40%. if the voltage finally forward biases the internal zener diode, then care must be taken to avoid injecting a current beyond ?2 ma. given the value of r oppu , there is no risk in the present example. finally, please note that another comparator internally fixes the maximum peak current set point to value v limit even if the opp pin is adversely biased above 0 v. frequency foldback the reduction of no?load standby power associated with the need for improving the efficiency, requires a change in the traditional fixed?frequency type of operation. this controller implements a switching frequency foldback when the feedback voltage passes below a certain level, v fold(start) . at this point, the oscillator turns into a voltage?controlled oscillator (vco) and reduces switching frequency down to f trans value, till to feedback voltage reaches the level v fold(end) . below this level v fold(end) , the frequency is fixed and cannot go further down. the peak current setpoint is following the feedback pin until its level reaches v fb(freeze) . below this value, the peak current setpoint is frozen to v cs(freeze) value or 31% of the maximum v limit setpoint. the only way to further reduce the transmitted power is to enter skip cycle, which is set when the feedback voltage reaches the level v skip . skip cycle offers the best noise?free performance in no?load conditions. figure 49 and depicts the adopted scheme for the part. fb frequency peak current setpoint v fb f sw v fb v cs f osc(nom) f trans v skip v fold(end) v fold(start) v fb(open) v limit v cs(fold) v cs(freeze) v skip v fb(freeze) v fold(start) min max v fb(limit) v fb(limit) figure 49. by observing the voltage on the feedback pin, the controller reduces its switching frequency for an improved performance at light load. v fb [v] t open loop skip mode i peak , max i peak , min peak current is frozen peak current is clamped peak current is chang ing f osc(nom) f trans f sw is fixed to f osc(nom) f sw is changing v skip v fold(end) v fold(start) v fb(open ) v fb(freeze ) v fb(limit) figure 50. another look at the relationship between feedback and current setpoint while in frequency reduction mode.
ncp12510 www. onsemi.com 19 auto?recovery short?circuit protection in case of output short?circuit or if the power supply experiences a severe overloading situation, an internal error flag is raised and starts a countdown fault timer. if the uvlo has come or the flag is asserted longer than fault timer value t fault (depends on chosen option), the driving pulses are stopped and the v cc falls down as the auxiliary pulses are missing. when it crosses v cc(min) , the controller consumption is down to a few a and the v cc slowly builds up again thanks to the resistive starting network. when v cc reaches v cc(on) , the controller purposely ignores the re?start and waits for another v cc cycle: this is the so?called double hiccup auto?recovery mode. by lowering the duty ratio in fault condition, it naturally reduces the average input power and the rms current in the output cable. illustration of such principle appears in figure 51. please note that soft?start is activated upon re?start attempt. t t v cc (t) v drv (t) v cc(on) v cc(min) t t error flag v cs (t) v limit overload -> start fault timer -> timer elapsed -> auto-recovery fault timer has elapsed short-circuit -> start timer -> error flag + uvlo -> auto-recovery fault timer has elapsed ss figure 51. an auto?recovery double hiccup mode is entered in case a faulty event longer than programmable fault timer value is acknowledged by the controller. latched short?circuit protection with pre?short in some applications, the controller must be fully latched in case of an output short circuit presence. in that case, you would select a controller with an ocp latched option in the options table. when the error flag is asserted, meaning the controller is asked to deliver its full peak current, the controller latches off upon timer completion: all pulses are immediately stopped and v cc hiccups between the two voltage levels, given by a v cc(min) level and added hysteresis v cc(latch_hyst) , until a reset occurs ( v cc falls down below v cc(reset) ). however, in presence of a small vcc capacitor, it can very well be the case where the stored energy does not give enough time to let the timer elapse before v cc touches the uvlo. when this happens, the latch is not acknowledged since the timer countdown has been prematurely aborted. to avoid this problem, ncp12510 (with latched ocp&uvlo option) combines the armed flag assertion together with the uvlo event to confirm a pre?short situation: upon start?up with first drive pulse, the armed flag is raised until regulation is met. if during the time the flag is raised an uvlo event is detected, the part latches off immediately. when ic is latched, v cc enters hiccup mode. in normal operation, if an uvlo event is detected for any reason, the controller will naturally resume operations. details of this behavior are given in figure 52. uvlo latch is made available solely during the start?up sequence. when the power supply starts?up, the armed flag is asserted with the first drive pulse. if an uvlo event occurs when the armed flag is asserted, the part immediately latches off. if no uvlo occurs, once the output voltage has reached regulation after 8 consecutive cycles, the internal armed flag is released and the latch authorizing uvlo detections is reset: any new uvlo events will simply be ignored. in the latched option ocp&uvlo, the uvlo test is available at the first power?up or when the part recovering from double hiccup mode.
ncp12510 www. onsemi.com 20 t t v cc (t) v drv (t) v cc(on) v cc(min) v cc(reset) t t flag v cs (t) v limit uvlo@start-up and armed flag latched new sequence glitch resumed 0 1 1 8 cycles resumed no armed flag uvlo@recovering and armed flag latched uvlo after regulation 8 cycles v cc(latch_hyst) figure 52. full latch occurs in case the uvlo@start?up or @recovering is detected while the armed flag is a sserted armed t t v cc (t) v drv (t) v cc(on) t t error flag v cs (t) v limit 0 1 8 cycles fault timer has elapsed flag latched latched when the ic is latched, the user have to unplugged and plugged the adapter to the outlet restart uvlo@start-up and armed flag ss armed flag error flag v cc(min) v cc(reset) v cc(latch_hyst) the v cc hysteresis in latch mode significantly improves the reset time . figure 53. full latch occurs in case the fault timer has elapsed or uvlo@start?up is detected with asserted armed flag. armed
ncp12510 www. onsemi.com 21 operation with grounded feedback pin the ncp12510 offers the operation mode when the ncp12510 could be controlled by master system via feedback pin (pin 2). when fb pin is grounded, the controller driver pulses are stopped. this is the same situation, when the controller is in skip mode, but with the difference that fb pin could be forced to ground by master system anytime during operation, even at start?up sequence. when the v cc touches v cc(on) level, the controller internal logic starts and thus, first drv pulse is authorized after the safety period of 200 s passes. but the last drv pulse can comes just before v cc(min) level. therefore, there are extended rules to generation and cancellation the armed flag to avoid the false pre?short condition if the controller can?t start properly because of the grounded fb pin. t t v cc (t) v drv (t) v cc(on) v cc(reset) t t armed flag v cs (t) v limit uvlo@start-up and armed flag latched new sequence 0 1 t v fb (t) uvlo@start-up and armed flag 1 grounded fb@v cc(on) no armed flag latched new sequence fb@ gnd 1 latched fb@gnd uvlo and armed flag grounded fb @first going- down v cc cycle double hiccup switching allowed every odd v cc(on) v cc(min) v cc(latch_hyst) figure 54. the controller start?up sequence with grounded fb pin and pre?short condition. t t v cc (t) v drv (t) v cc(on) v cc(min) v cc(reset) t t armed flag v cs (t) v limit 0 t v fb (t) 1 1 uvlo and no armed flag auto-recovery 8 cycles new sequence 1 1 uvlo and no armed flag auto-recovery 8 cycles fb@ gnd fb@ gnd fb@ gnd fb@ gnd 1 auto-recovery uvlo figure 55. the controller behaviour during start?up sequence interupted by grounded fb pin.
ncp12510 www. onsemi.com 22 the armed flag is generated with first drv pulse, but only if the first drv pulse is synchronized with v cc(on) event. if the fb pin is forced to ground during the v cc(on) event and it is released afterwards, the armed flag is not generated. the figure 54 shows the cases of grounded fb pin at the beginning of start?up sequence. if the armed flag isn?t active and uvlo comes, the controller newly starts after double?hiccup auto?recovery sequence. then, if uvlo comes again, the controller is latched off. drv pulses are authorized during the whole first v cc going?down cycle. if any drv pulse doesn?t come during this time, the double?hiccup auto?recovery sequence is coming. the armed flag could be canceled by two conditions. when the controller gets into regulation after start?up sequence, i.e. during the eight consecutive switching cycles is current setpoint voltage under v limit , the armed flag is called off ? this is the first armed flag cancelation condition. when the start?up sequence isn?t complete and is interrupted by grounded fb pin, the armed flag is called off ? this is the second armed flag cancelation condition. the figure 55 shows the cases of interrupted start?up sequence by grounded fb pin. if the start?up sequence is interrupted by grounded fb pin, the armed flag is canceled. then, if uvlo comes, the controller newly starts after double?hiccup auto?recovery sequence. then, if uvlo comes again, the controller is latched off. the figure 56 shows the case of operation, when the controller can operate under some master system with superordinate function. then, the fb pin is used for authorization or denial drv pulses. if the normal operation state is interrupted for a long time and afterwards the soft?start is demanded for proper start?up of power supply, the v cc have to be pulled?down below v cc(reset) level. then, if the fb isn?t grounded, the new start?up sequence are initialized when v cc touches v cc(on) level + 200 s safety period. during this new start?up sequence is generated the armed flag. t t v cc (t) v drv (t) v cc(on) v cc(min) v cc(reset) t t flag v cs (t) v limit 0 t v fb (t) 1 8 cycles new sequence fb@ gnd 8 cycles fb@ gnd stop drv pulses by master sytem supply voltage v cc is controlled by master system fb@ gnd the ic must be reset to ensure the soft -start after release the fb 8 cycles 1 grounded fb @v cc(on) no armed flag figure 56. the master system driving the controller by forcing the fb pin to ground. armed slope compensation the ncp12510 includes an internal slope compensation signal. this is the buffered oscillator clock delivered during the on?time only. its amplitude is around 2.5 v at the maximum duty ratio. slope compensation is a known means used to cure sub harmonic oscillations in ccm?operated current?mode converters. these oscillations take place at half the switching frequency and occur only during continuous conduction mode (ccm) with a duty ratio greater than 50%. to lower the current loop gain, one usually injects between 50 and 100% of the primary inductance downslope. figure 57 depicts how the ramp is generated internally. please note that the ramp signal will be disconnected from the cs pin during the off?time.
ncp12510 www. onsemi.com 23 0v 2.5 v t leb + _ cs r comp r sense 20 k? on time from fb driver reset t sw d max r ramp figure 57. inserting a resistor in series with the current sense information brings slope compensation and stabilizes the converter in ccm operation. in the ncp12510 controller, the oscillator ramp features a 2.5 v swing. if the clock operates at a 65 khz frequency, then the available oscillator slope corresponds to: s ramp v ramp,peak d max t sw 2.5 0.8 15 208 mv s (eq. 10 ) in our flyback design, let?s assume that our primary inductance l p is 770 h, and the smps delivers 19 v with a n p : n s ratio of 1:0.25. the off?time primary current slope s p is thus given by: s p v out v f
n s n p l p ( 19 0.7 ) 4 770 102 ma s (eq. 11) given a sense resistor of 330 m , the above current ramp turns into a voltage ramp of the following amplitude: s sense s p r sense 102 m 0.33 34 mv s (eq. 12) if we select 50% of the downslope as the required amount of slope compensation, then we shall inject a ramp whose slope is 17 mv/ s. our internal compensation being of 208 mv/ s, the divider ratio ( divratio ) between r comp and the internal r ramp = 20 k resistor is: divratio 0.5 s sense s ramp 0.082 (eq. 13) the series compensation resistor value is thus: r comp r ramp divratio 20 k 0.082 1.64 k (eq. 14) a resistor of the calculated value will then be inserted from the sense resistor to the current sense pin. we recommend adding a small capacitor of 100 pf, from the current sense pin to the controller ground for an improved immunity to the noise. please make sure both components are located very close to the controller. latching off the controller the opp pin not only allows a reduction of the peak current set point in relationship to the line voltage, it also offers a means to permanently latch?off the part. when the part is latched?off, all pulses are immediately stopped and v cc hiccups from v cc(min) voltage level with hysteresis v cc(latch_hyst) until a reset occurs (v cc falls down below level v ccreset ), e.g. by un?plugging the converter from the mains outlet. the v cc latch hysteresis helps significantly reduce the reset time, because when the user unplugged the adapter from the outlet in the less favorable time (v cc is in its maximum), the v cc has to fall down from voltage level given by 550 mv + 300 mv typically to reset level. the latch detection is made by observing the opp pin by a comparator featuring a v latch reference voltage. however, for noise reasons and in particular to avoid the leakage inductance contribution at turn off, a blanking delay t latch?blank is introduced before the output of the ovp comparator is checked. then, the ovp comparator output is validated only if its high?state duration lasts for a minimum time t latch?del . below this value, the event is ignored. then, a counter ensures that only 4 successive ovp events have occurred be fore actually latching the part. there are several possible implementations, depending on the needed precision and the parameters you want to control. the first and easiest solution is the additional resistive divider on top of the opp one. this solution is simple and inexpensive but requires the insertion of a diode to prevent disturbing the opp divider during the on?time.
ncp12510 www. onsemi.com 24 t t t v latch v cc (t) v drv (t) v cc(on) v cc(min) v cc(reset) v latch (t) the ic is latched after the fault is confirmed for 4 consecutive drv cycles the user unplugged and plugged the adapter to the outlet v cc(latch_hyst) the time needs for ic reset is significantly shorter due to the v cc hysteresis used in latch mode . figure 58. latching off the controller and resuming operation. opp/ latch + v latch _ + r oppl c 1 100p v cc r oppu r ovp ovp opp aux. winding + d 1 figure 59. a simple resistive divider brings the opp pin above 3 v in case of a v cc voltage runaway above 18 v. first, calculate the opp network with the above equations. then, suppose we want to latch off our controller when v out exceeds 25 v. on the auxiliary winding, the plateau reflects the output voltage by the turns ratio between the power and the auxiliary winding. in case of voltage runaway for our 19 v adapter, the plateau will go up to: v aux,ovp v out n s n aux 25 0.18 0.25 18 v (eq. 15) since our ovp comparator trips at level v latch = 3 v, across the 1 k selected opp pull?down resistor, it implies a 3 ma current. from 3 v to go up to 18 v, we need an additional 15 v. under 3 ma and neglecting the series diode forward drop, it requires a series resistor of: r ovp v out v aux,ovp v latch v ovp r oppl 18 3 3 1k 5k (eq. 16) in nominal conditions, the plateau establishes to around 14 v. given the divide by 6 ratio, the opp pin will swing to 14/6 = 2.3 v during normal conditions, leaving 700 mv for the noise immunity. a 100 pf capacitor can be added to improve it and avoid erratic trips in presence of external surges. do not increase this capacitor too much otherwise the opp signal will be affected by the integrating time constant. a second solution for the ovp detection alone is to use a zener diode wired as recommended by figure 60. opp / latch + v latch _ + r oppl c 1 22p v cc r oppu ovp opp aux . winding + 15 v d 1 figure 60. a zener diode in series with a diode helps to improve the noise immunity of the system.
ncp12510 www. onsemi.com 25 in this case, to still trip at 18 v level, we have selected a 15 v zener diode. in nominal conditions, the voltage on the opp pin is almost 0 v during the off?time as the zener is fully blocked. this technique clearly improves the noise immunity of the system compared to that obtained from a resistive string as in figure 59. please note the reduction of the capacitor on the opp pin to 10?22 pf. this is because of the potential spike going through the zener parasitic capacitor and the possible auxiliary level shortly exceeding its breakdown voltage during the leakage inductance reset period (hence the internal blanking delay t latch?blank at turn off). this spike despite its very short time is energetic enough to charge the added capacitor c 1 and given the time constant, could make it discharge slower, potentially disturbing the blanking circuit. when implementing the zener option, it is important to carefully observe the opp pin voltage (short probe connections!) and check that enough margin exists to that respect. over temperature protection in a lot of designs, the adapter must be protected against thermal runaways, e.g. when the temperature inside the adapter box increases a certain value. figure 61 shows how to implement a simple otp using an external ntc and a series diode. the principle remains the same: make sure the opp network is not bothered by the additional ntc hence the presence of this diode. opp/ latch + v latch _ + r oppl v cc r oppu ovp opp aux. winding + ntc d 1 figure 61. the internal circuitry hooked to opp/latch pin can be used to implement over temperature protection (otp). when the ntc resistor will diminish as the temperature increases, the voltage on the opp pin during the of f?time will slowly increase and, once it passes v latch level for 4 consecutive clock cycles, the controller will permanently latch off. back to our 19 v adapter, we have found that the plateau voltage on the auxiliary diode was 14 v in nominal conditions. we have selected an ntc which offers a 470 k resistance at 25 c and drops to 8.8 k at 110 c. if our auxiliary winding plateau is 14 v and we consider a 0.7 v forward drop for the diode, then the voltage across the ntc in fault mode must be: v ntc v aux v latch v f 14 3 0.7 10.3 v (eq. 17 ) based on the 8.8 k ntc resistor at 110 c, the current inside the device must be: i ntc v ntc r ntc(110) 10.3 8.8 k 1.2 ma (eq. 18) as such, the bottom resistor r oppl , can easily be calculated: r oppl v latch i ntc 2.5 k (eq. 19) now the pull down opp resistor is known, we can calculate the upper resistor value r oppu to adjust the power limit at the chosen output power level. suppose we need a 200 mv decrease from the v limit setpoint and the on?time swing on the auxiliary anode is ?67.5 v, then we need to drop over r oppu a voltage of: v r oppu v aux v opp ?67.5 0.2 ?67.3 v (eq. 20 ) the current circulating the pull down resistor r oppl in this condition will be: i r oppl v opp r oppl ?0.2 2.5 k ?80 a (eq. 21) the r oppu value is therefore easily derived: r oppu v r oppu i r oppu ?67.3 ?80 841 k (eq. 22) combining ovp and otp the otp and zener?based ovp can be combined together as illustrated by figure 62. in nominal v cc /output conditions, when the zener is not activated, the ntc can drive the opp pin and trigger the adapter in case of a fault. on the contrary, in nominal temperature conditions, if the loop is broken, the voltage runaway will be detected and acknowledged by the controller. in case the opp pin is not used for either opp or ovp, it can simply be grounded.
ncp12510 www. onsemi.com 26 opp / latch + v latch _ + r oppl v cc r oppu ovp opp aux. winding + ntc 15 v d 1 figure 62. with the ntc back in place, the circuit nicely combines ovp, otp and opp on the same pin. filtering the spikes the auxiliary winding is the seat of spikes that can couple to the opp pin via the parasitic capacitances exhibited by the zener diode and the series diode. to prevent an adverse triggering of the over voltage protection circuitry, we recommend the installation of a small rc filter before the detection network as illustrated by figure 63. the values of resistance and capacitance must be selected to provide the adequate filtering function without degrading the stand?by power by an excessive current circulation. opp/ latch + v latch _ + r oppl v cc r oppu ovp opp aux. winding + ntc 15 v d 1 r 1 c 1 additional filter figure 63. a small rc filter prevents the fast rising spikes from reaching the protection pin opp/latch in presence of energetic perturbations superimposed on the input line.
ncp12510 www. onsemi.com 27 package dimensions case 318g?02 issue v 23 4 5 6 d 1 e b e1 a1 a 0.05 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. maximum lead thickness includes lead finish. minimum lead thickness is the minimum thickness of base material. 4. dimensions d and e1 do not include mold flash, protrusions, or gate burrs. mold flash, protrusions, or gate burrs shall not exceed 0.15 per side. dimensions d and e1 are determined at datum h. 5. pin one indicator must be located in the indicated zone. c *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* dim a min nom max millimeters 0.90 1.00 1.10 a1 0.01 0.06 0.10 b 0.25 0.38 0.50 c 0.10 0.18 0.26 d 2.90 3.00 3.10 e 2.50 2.75 3.00 e 0.85 0.95 1.05 l 0.20 0.40 0.60 0.25 bsc l2 ? 0 1 0 1.30 1.50 1.70 e1 e recommended note 5 l c m h l2 seating plane gauge plane detail z detail z 0.60 6x 3.20 0.95 6x 0.95 pitch dimensions: millimeters m style 13: pin 1. gate 1 2. source 2 3. gate 2 4. drain 2 5. source 1 6. drain 1 on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does o n semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including ?typic als? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distrib utors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ncp12510/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative ?

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